Lianfeng Yang

 Device Modelling Group
 Room 305, Rankine Building, Oakfield Avenue
 Department of Electronics and Electrical Engineering
 University of Glasgow
 Glasgow G12 8LT, UK

 Tel   : +44-141-330 4792
 Fax   : +44-141-330 4907
 Email : lfyang@elec.gla.ac.uk
         lfyang@ieee.org/lfyang@gmail.com
 Web   : http://www.elec.gla.ac.uk/~lfyang/

 

 In China:

 Tel: +86-13691400006

 Email: lfyang@ieee.org/lfyang@gmail.com

 Web  : http://www.elec.gla.ac.uk/~lfyang/

It's me!



From October 2001 to July 2004, I worked as a full-time Ph.D research student in the Device Modelling Group of the Department of Electronics and Electrical Engineering at the University of Glasgow, under the supervisions of Prof. John R. Barker and Prof. Asen Asenov, fully funded by one of the largest EPSRC grants -- "SiGe MOSFET Technology: phase II (2001-2004)". I passed my Ph.D viva in September 2004. I came from Jiangsu, China, where I have enjoyed seven years in the most beautiful city - Nanjing until Oct. 2001 and received my M.Sc and B.Sc degrees from Southeast University.

 

Since July 2004, I moved back to Beijing, China and started my career in the Beijing R&D Center of Cadence Design Systems Inc., as a Sr. Product Engineer working on compact modelling.

 

R&D experience

 

2       Simulation study of advanced sub-100nm MOSFETs for RF and CMOS applications (Ph.D Project), 10/2001-09/2004:

Ø          Project description (Funded by the UK Engineering and Physical Science Research Council):

·         Scaling study of strained-Si/SiGe modulation doped FETs (MODFET) for RF applications

·         Optimization of sub-100nm strained-Si/SiGe MODFETs for high linearity applications

·         Prediction of device and circuit behavior of scaled sub-100nm strained Si CMOS

·         Investigation of the impact of interface roughness on the performance enhancement of strained Si MOSFETs over Si devices

·         Study of the mobility degradation mechanism in Si and strained Si MOSFETs with high-κ gate dielectrics due to soft optical phonon scattering

·         Design and simulation of high-speed III-V MOSFETs for digital applications

·         Published over 20 papers in international journals and conferences

Ø          Simulation tools used in the project:

·         Synopsys TCAD tools (TSUPREM, MEDICI, TAURUS, etc), 1-D Poisson-Schrödinger solver, in-house ensemble full-band Monte Carlo simulator

Ø          Programming:

·         FORTRAN programming for RF extraction and scattering modules in Monte Carlo simulator

2       Integrated Circuit design, 9/1999-10/2001

Ø           4bit MCU for personal Databank (0.8micron process), 5/2000-10/2001 (as Project manager)

Ø           A series of STN LCD drivers for mobile phone (0.6micron HV process), 1/2000-6/2001 (as Project manager)

Ø           DC/DC converter (2micron BiCMOS), 9/1999-12/1999 (as Project manager)

 

2       Study of semiconductor device numerical simulation techniques, 03/1997-12/1999

Ø          Project description (Funded by China 9th five-year-plan Key Technology R&D Program and National Natural Science Foundation of China):

·  As a team leader, developed a MOS/BJT numerical device simulator using C++

·  Proposition and verification of a parallel device simulation technique based on a distributed network environment

·  Published over 10 papers in Chinese technical journals and conferences

 

PUblications

 

Ph.D Thesis

 

2       L. Yang. "Numerical simulation of sub-100nm strained Si/SiGe MOSFETs for RF and CMOS applications", University of Glasgow, 2004.

 

Journal Papers (as of September 2004)

 

2       L. Yang, J. R. Watling, R. C. W. Wilkins, M. Borici, J. R. Barker, A. Asenov and S. Roy. "Surface roughness in sub-100nm Si and strained Si MOSFETs – A Monte Carlo study", submitted to IEEE Transaction on Electron Devices, 2004.

2       L. Yang, J. R. Watling, R. C. W. Wilkins, M. Borici, J. R. Barker, A. Asenov and S. Roy. "Si/SiGe heterostructure parameters for device simulations", Semiconductor Science and Technology, 19(10), p1174-1182, 2004.

2       L. Yang, A. Asenov, J. R. Watling, M. Borici, J. R. Barker, S. Roy, K .Elgaid, I. Thayne and T. Hackbarth. "Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs", Microelectronics Reliability, 44(7), p1101-1107, 2004.

2       J. R. Watling, L. Yang, M. Borici, R. C. W. Wilkins, A. Asenov, J. R. Barker and S. Roy. "The impact of interface roughness scattering and degeneracy in relaxed and strained Si n-channel MOSFETs", Solid State Electronics, 48, p1337-1346, 2004 (invited).

2       K. Kalna, M. Borici, L. Yang and A. Asenov, "Monte Carlo simulation of III-V MOSFETs", Semiconductor Science and Technology, 19S, p202-205, 2004.

2       L. Yang, J. Watling, M. Borici, R. C. W. Wilkins, A. Asenov, J. R. Barker and S. Roy, "Simulations of scaled sub-100nm strained Si/SiGe p-channel MOSFETs", Journal of Computational Electronics, 2, p363-368, 2004.

2       J. R. Watling, L. Yang, M. Borici, J. R. Barker and A. Asenov, "Degeneracy and high doping effects in deep sub-micron relaxed and strained Si n-MOSFETs", Journal of Computational Electronics, 2, p475-480, 2004.

2       M. Borici, J. R. Watling, R. C. W. Wilkins, L. Yang, J. R. Barker and A. Asenov, Interface roughness scattering and its impact on electrons transport in relaxed and strained Si n-MOSFETs, Semiconductor Science and Technology, 19S, p155-157, 2004.

2       K. Kalna, L. Yang and A. Asenov, Simulation study of high performance III-V MOSFETs for Digital Applications, Journal of Computational Electronics, 2, p341-346, 2004.

2       M. Borici, J. R. Watling, R. C. W. Wilkins, L. Yang and J. R. Barker, A Non perturbative model of surface roughness scattering for Monte Carlo simulation of relaxed Silicon n-MOSFETs, Journal of Computational Electronics, 2, p163-168, 2004.

2       Lianfeng Yang, Jin Wu and Tongli Wei. The system design of semiconductor device simulation, Journal of Southeast University. (English Edition), 1999, Vol. 15, No.4.

 

2       Conferences (as of September 2004)

 

2       L. Yang, J. R. Watling, F. Adam-Lema, A. Asenov and J. R. Barker, "Scaling study of Si and strained Si n-MOSFETs with different gate stacks". To appear in the 2004 IEEE International Electron Device Meeting (IEDM), San Francisco, December 2004.

2       J. R. Watling, L. Yang, A. Asenov, J. R. Barker and S. Roy, Impact of high-κ dielectric HfO2 on the mobility and device performance of sub-100nm n-MOSFETs. To appear in the 2004 International Workshop on Electrical Characterization and Reliability of High-κ Devices, Austin, November 2004. (to be published in the IEEE Transaction on Device and Material Reliability)

2       L. Yang, J. R. Watling, F. Adam-Lema, A. Asenov and J. R. Barker, "Simulations of scaled strained Si MOSFETs with high-κ gate stacks". To appear in the 10th IEEE International Workshop of Computational Electronics (IWCE), Indiana, October 2004. (to be published in Journal of Computational Electronics)

2       L. Yang, J. R. Watling, A. Asenov, J. R. Barker and S. Roy, "Sub-100nm strained Si CMOS: Device performance and circuit behavior". To appear in the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, October 2004.

2       L. Yang, J. R. Watling, A. Asenov, J. R. Barker and S. Roy. "Device performance in conventional and strained Si MOSFETs with high-κ gate stack". Proceeding of the 2004 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p199-202, Springer-Verlag, 2004.

2       L. Yang, J. R. Watling, J. R. Barker and A. Asenov. "The impact of soft-optical phonon scattering due to high-κ dielectrics on the performance of sub-100nm conventional and strained Si n-MOSFETs". Presented in the 27th International Conference on Physics of Semiconductors (ICPS27), Arizona, 2004.

2       L. Yang, J. R. Watling, R. C. W. Wilkins, J. R. Barker and A. Asenov, "Reduced interface roughness in sub-100nm strained Si n-MOSFETs - A Monte Carlo simulation study", Proceedings of the 5th Europe Workshop on Ultimate Integration of Silicon (ULIS04), p23-26, IMEC, 2004.

2       K. Kalna, L. Yang, J. R. Watling, A. Asenov, 80nm InGaAs MOSFET compared to equivalent Si transistor, Proceedings of the 5th Europe Workshop on Ultimate Integration of Silicon (ULIS04), p159-162, IMEC, 2004.

2       L. Yang, J. R. Watling, R. C. W. Wilkins, J. R. Barker and A. Asenov. Monte Carlo investigation of interface roughness scattering in relaxed and strained Si n-MOSFETs, presented at the IoP Condensed Matter and Materials Physics Conference (CMMP04), Warwick, 2004.

2       J. R. Watling, L. Yang, J. R. Barker and A. Asenov. The Impact of high-κ dielectrics on the future performance of nano-scale MOSFETs, presented at the IoP Condensed Matter and Materials Physics Conference (CMMP04), Warwick, 2004.

2       L. Yang, A. Asenov, M. Borici, J. R. Watling, J. R. Barker, S. Roy, K .Elgaid, I. Thayne and T. Hackbarth. Optimizations of sub-100nm Si/SiGe MODFETs for high linearity RF applications, Proceedings of the 2003 IEEE Conference on Electron Device and Solid-State Circuits (EDSSC03), p331-334, Hong Kong, 2003.

2       L. Yang, A. Asenov, J. R. Watling, M. Borici, J. R. Barker, S. Roy, K .Elgaid, I. Thayne and T. Hackbarth. A simulation study of high linearity Si/SiGe HFETs, Proceedings of the 14th Workshop on Modelling and Simulation of Electron Device (MSED03), p41-44, Barcelona, 2003.

2       L. Yang, J. Watling, M. Borici, R. C. W. Wilkins, A. Asenov, J. R. Barker and S. Roy. Simulations of scaled sub-100nm strained Si/SiGe p-channel MOSFETs, presented at the 9th IEEE International Workshop of Computational Electronics (IWCE), Rome, 2003.

2       L. Yang, J. R. Watling, R. C. W. Wilkins, A. Asenov, J. R. Barker, S. Roy and T. Hackbarth. Scaling study of Si/SiGe MODFETs for RF applications, presented at the 10th Advanced Heterostructure Workshop (AHW02), Hawaii, 2002.

2       L. Yang, J. R. Watling, R. C. W. Wilkins, A. Asenov, J. R. Barker, S. Roy and T. Hackbarth. Scaling study of Si/SiGe MODFETs for RF applications, Proceeding of the 10th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications (EDMO02), p101-106, Manchester, 2002.

2       K. Kalna, L. Yang and A. Asenov. High Performance III-V MOSFETs: a Dream Close to Reality?, Proceeding of the 10th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications (EDMO02), p243-248, Manchester, 2002.

2       Lianfeng Yang, Jin Wu, Nasirjiang and Tongli Wei, The Parallel Simulation Software Design Method On Hydrodynamic Model, Proceeding of 1998 IEEE Hong Kong Electron Devices Meeting, p134-137, Hong Kong, 1998.

2       Yang Lianfeng, Jin Wu, Nasirjiang and Tongli Wei. The development of Deep Sub Micrometer Semiconductor Devices Simulation based on the CORBA platform, Proceeding of 5th International Conference on Solid-State Integrated-Circuit Technology (ICSICT’98), p443-446, Beijing, 1998.

 

2       Journal Papers in Chinese (Selected)

 

2       Yang Lianfeng, et al.. The Design of a STN LCD Driver, Microelectronics, 31(1), p53-57, 2001 (ISSN 1004-3365).

2       Yang Lianfeng, et al.. The Design and Realization of a Submicron Device Simulator for SiGe HBT, Research & Progress of Solid-State Electronic, 21(3), p313-319, 2001(ISSN1000-3819).

2       Yang Lianfeng, et al.. SMDS-A Semiconductor Device Simulator designed by Object-oriented Technology, Acta Electronica Sinica. (Dian Zi Xue Bao), 28(2), p62-64, 2000 (ISSN 0372-2112).

2       Yang Lianfeng, et al., A semiconductor parallel simulation technology under network distributed platform, Research & Progress of Solid-State Electronic, 20(4), p378-383, 2000(ISSN1000-3819).

2       Yang Lianfeng, et al.. Mixed-Signal HDL language, The Sixth Youth Conference of Chinese Institute Electronics (CIE-YC’2000), Wuxi China, 2000.

 

 

Education & employment HISTORY

 

2         July, 2004 – present: Sr. Product Engineer, Beijing R&D Center, Cadence Design Systems Inc.

2         Oct., 2001– June, 2004: Dept. of Electronics and Electrical Engineering, University of Glasgow, UK.

                                                                     Research topic: Device simulations of sub-100nm strained Si/SiGe FETs

                                                                     Degree expected: Ph.D (Oct. 2004).

2         Apr., 2000– Oct., 2001: R&D manager, Beijing Procomic Device Co. (Nanjing R&D Centre)

2         Sep., 1999 – Oct., 2001: Deputy Manager, Nanjing Tuoke Tech. Ltd, China

2         Sep., 1998 – Apr., 2000: Dept. of Electronics Engineering, Southeast University, China.

                                                                     Major: Microelectronics & Solid Electronics

                                                                     Thesis: The study of Parallel Simulation for Semiconductor Devices

                                                                     Degree obtained: M.S.

2         Sept., 1996 – Jul., 1998: Dept. of Electronics Engineering, Southeast University, China.

                                                                     Major: Microelectronics Technology

                                                                     Degree obtained: B.S.

2         Sept., 1994 – Jul., 1996: 94 Intensive Class (Class for talented), Southeast University, China.

 

PROFESSIONAL AFFILIATION

 

2       Student Member, IEEE Solid-State Circuit Society and Electron Device Society, 1999-present

 

HONORS (SELECTED)

 

2       Xin-Tian-Xia Scholarship, Southeast University, 2000

2       Oriented Communications Scholarship, Southeast University, 1999

2       The Award of Best Graduate-Project of Southeast University, 1998

2       The first prize in China Undergraduate Mathematical Contest in Modeling, as director, 1998

2        The Meritorious Award of America Mathematical Contest in Modeling, 1998 (international)

2       The first prize in China Undergraduate Mathematical Contest in Modeling, 1997

2       The first in Mathematical Contest in Modeling of Southeast University, 1996

2       First Prize General fellowship (top 10% in university), Southeast University, 1994

 

Last updated: 30 September, 2004